Description

Energy efficiency has become a critical challenge in modern computing, from embedded IoT devices to high-performance supercomputers. Conventional CMOS-based architectures are reaching fundamental limits, including the end of Dennard scaling, rising static power dissipation, and the “memory wall” — data transfers between processor and memory alone account for 70 to 90% of a system’s total energy budget. In-Memory Computing (IMC) is emerging as a compelling solution by embedding computation directly within memory arrays, thereby eliminating costly data movements. In this context, ferroelectric field-effect transistors (FeFETs) stand out as particularly attractive devices: they are compatible with standard CMOS fabrication processes, inherently non-volatile, and enable reconfigurable logic gates in which one operand is persistently encoded in the ferroelectric gate stack — a concept already demonstrated at INL.

This PhD thesis is carried out within the ANR eCAT project (Enabling Computer Architecture for Tomorrow), a 2025 Franco-German PRCI collaboration involving INL, Inria Rennes, Heidelberg University, and TU Dresden. The project targets a complete heterogeneous architecture ecosystem combining RISC-V processors, FeFET-based IMC units, Near-Memory Computing (NMC), and Approximate Computing (AxC). INL leads the circuit design and device characterization workpackages.

The central scientific contribution of this PhD is the exploration of ternary logic implemented through ferroelectric devices. Unlike conventional binary logic, ferroelectric materials can be programmed into stable intermediate polarization states, enabling a natural three-valued logic (0, 1, 2) within a single device. This property opens new avenues for higher integration density, reduced interconnect complexity, and greater logical expressiveness per device.

The thesis unfolds in two main phases. In the first phase, the candidate will investigate the programming conditions required to reliably achieve and maintain stable intermediate ferroelectric polarization states, then design and characterize a library of elementary ternary logic gates — including ternary inverters, MIN/MAX gates, and comparators — evaluated in terms of delay, energy consumption, and endurance, using industrial EDA tools such as Cadence Virtuoso/Spectre and Synopsys. In the second phase, the work scales up to ternary arithmetic operators (adders, multipliers) targeting eCAT application workloads, with a particular focus on convolutional neural networks. Approximate computing will also be explored through deliberate modulation of the ferroelectric programming scheme, trading off precision for further energy gains. The resulting circuit models will be abstracted at multiple levels of representation and integrated into the project’s system-level simulator to quantify real-world improvements in energy efficiency, computational precision, and throughput.

The ideal candidate holds a Master’s degree in microelectronics or a related field, with solid expertise in digital circuit design flows, semiconductor device physics, and hardware description languages (Verilog-A, VHDL, or Verilog). Familiarity with non-volatile memory technologies or ferroelectric materials is a strong asset. The position requires scientific rigor, autonomy, and the ability to collaborate within an international research consortium. Fluency in scientific English is mandatory.

The PhD will be hosted at INL (UMR CNRS 5270), a multidisciplinary nanotechnology research unit affiliated with CNRS, École Centrale de Lyon, INSA Lyon, Université Lyon 1, and CPE Lyon, gathering approximately 200 researchers across two campuses in the Lyon area.

Compétences requises

Formation Académique Master en microélectronique, génie électrique ou dans un domaine connexe. Compétences Techniques • Conception de circuits : Maîtrise des flots de conception numérique (schématique, simulation, synthèse) à l’aide d’outils EDA industriels, de préférence Cadence Virtuoso/Spectre et Synopsys. • Physique des composants : Solides connaissances en physique des dispositifs semiconducteurs et MOS ; une expérience préalable en mémoires non volatiles ou en matériaux ferroélectriques constitue un atout. • Logique numérique : Curiosité pour les paradigmes logiques non conventionnels tels que la logique multi-valuée et le calcul approximatif, ainsi que pour les nouvelles architectures mémoire. • Programmation et simulation : Maîtrise des langages de description matérielle (Verilog-A, VHDL ou Verilog) ; la programmation Python pour l’automatisation des simulations est un atout supplémentaire. Compétences Transversales • Rigueur scientifique et autonomie intellectuelle. • Capacité à travailler efficacement au sein d’un environnement collaboratif international, avec des interactions régulières avec les partenaires français et allemands du projet eCAT. Langue La maîtrise de l’anglais scientifique (lecture, rédaction et présentation orale) est obligatoire. En résumé, le candidat idéal allie une solide formation en microélectronique et en physique des composants à une expérience pratique en conception de circuits, un intérêt marqué pour les paradigmes de calcul émergents, ainsi que les compétences en communication nécessaires pour s’épanouir dans un projet de recherche international. Application (CV including academic transcripts, cover letter) MUST be submitted through the following platform: https://ecolecentraledelyon.recruitee.com/o/centrale-lyon-doctorant-conception-de-circuit-ferroelectrique-pour-la-logique-ternaire/c/new?lang=en

Bibliographie

[1] M. Jerry et al., “Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 27, no. 1, pp. 159–172, Jan. 2019.

[2] K. Ni et al., “A Circuit Compatible Accurate Compact Model for Ferroelectric-FETs,” in Proc. IEEE Symp. on VLSI Technology, Honolulu, HI, USA, 2018, pp. 131–132.

[3] C. Marchand et al., “FeFET based Logic-in-Memory: an overview,” in Proc. IEEE 14th Int. Conf. on Design & Technology of Integrated Systems in Nanoscale Era (DTIS), Hammamet, Tunisia, 2021, pp. 1–6.

[4] S. Kim et al., “A Logic Synthesis Methodology for Low-Power Ternary Logic Circuits,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 9, pp. 3138–3151, Sep. 2020.

[5] S. K. Thirumala et al., “Ternary Compute-Enabled Memory Using Ferroelectric Transistors for Accelerating Deep Neural Networks,” in Proc. Design, Automation & Test in Europe (DATE), Grenoble, France, 2020, pp. 1–6.

Mots clés

Logique ternaire, Dispositifs ferroélectriques , Calcul en mémoire (IMC) , Conception de circuits intégrés