Description

Working in a collaborative academic project, your task will be to develop a smart image sensor for a wireless camera network embedding distributed AI computing. Current camera network contains several standard cameras that transmit their images to a global server performing the targeted inference processing. This kind of architecture proposes energy and frugality performances that are not compatible with IoT requirements. The project goal is to tackle hardware frugality through a distributed and collaborative approach based on ultra-low-power computing nodes. Each node’s inference core will be built around ASIC processors performing calculations in analog form. The final demonstrator will consist of a wireless network of “motes” (sensor network nodes) integrating dedicated image sensors paired with hybrid processors performing analog processing. In this context, the mote’s image sensor must extract strategic features with frugality and efficiency which implies that you have to define, design and test an innovative readout architecture of a standard imager. In collaboration with the academic partners, you will be involved in the definition of the overall mote architecture allowing to define basically the output data format and the output procedure of the imager including potential pre-processing for the distributed inference computations. The studied architecture will integrate innovative low power solutions to address the targeted IoT applications and perform both image acquisitions and AI pre-processing. As an image sensor demonstrator is planned in this PhD Thesis, the work will be conducted at CEA-Leti in the L3i Laboratory, using professional IC design tools and software development environments.