Description

Join CEA-Leti and CROMA to analyze in depth junctions of a new technology. Our transistors are fabricated under restricted thermal budget for 3D sequential integration, making dopants activation very challenging! Our team will support you technically and scientifically to conduct this work. Some data are already available and waiting for your analysis.
During this PhD, you will have the opportunity to characterize in depth a
From the idea (simulation, bibliography, TCAD) 20%
Processes understanding (implantation, SPER) 10%
Integration & cleanroom fabrication management 10%
Characterization (physical & electrical: noise, DLTS…) 50%
Valorization (presentations, article) 10%
This PhD offers a unique chance to be at the forefront of technological innovation and to make a significant impact in the field of advanced SOI. Join us and take the first step towards an exciting career in research and development!

Skills required

With a background in microelectronics or nanotechnologies, you are curious about integration of new processes, not afraid about equations and liked semiconductors classes at school. You want to solve complex puzzles and enjoy collaborating with others to figure out innovative solutions.

Bibliography

[1] P. Batude et al., 'Opportunities and challenges brought by 3D-sequential integration,' 2021 IEEE International Interconnect Technology Conference (IITC), Kyoto, Japan, 2021, pp. 1-1, doi: 10.1109/IITC51362.2021.9537356.
[2] S. Reboh et al., 'NanoStack Transistor Architecture for CMOS 7A Node and Beyond,' 2025 Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Kyoto, Japan, 2025, pp. 1-3, doi: 10.23919/VLSITechnologyandCir65189.2025.11074866.
[3] F. Guyader et al., '3-Tier BSI CIS with 3D Sequential & Hybrid Bonding Enabling a1.4um pitch,106dB HDR Flicker Free Pixel,' 2022 International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 37.4.1-37.4.4, doi: 10.1109/IEDM45625.2022.10019432.
[4] K. Nakazawa et al., '3D Sequential Process Integration for CMOS Image Sensor,' 2021 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2021, pp. 30.4.1-30.4.4, doi: 10.1109/IEDM19574.2021.9720563.
[5] D. Bosch et al., 'High Performance 2.5V n&p 400°C SOI MOSFETs: a Breakthrough for versatile 3D Sequential Integration,' 2025 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2025, pp. 1-4, doi: 10.1109/IEDM50572.2025.11353514
[6] D. Bosch et al., 'Breakthrough Processes for Si CMOS Devices with BEOL Compatibility for 3D Sequential Integrated more than Moore Analog Applications,' 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), Honolulu, HI, USA, 2024, pp. 1-2, doi: 10.1109/VLSITechnologyandCir46783.2024.10631398.

Keywords

MOSFET, Electrical Characterization, Physical modelling, Semiconductor device physics, Defects in semiconductors, Microelectronic